1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a buffer of the semiconductor memory apparatus.
2. Related Art
A general buffer includes first to fifth transistors P1, P2, and N1 to N3 as shown in FIG. 1. The first transistor P1 is applied with an external voltage VDD at a source thereof. A gate of the second transistor P2 is connected to a gate of the first transistor P1 and is applied with the external voltage VDD at a source thereof. The third transistor N1 receives an inverted input signal ‘inb’ at a gate thereof and a drain of the third transistor N1 is connected to the gate and a drain of the first transistor P1. The fourth transistor N2 receives an input signal ‘in’ at a gate thereof and a drain of the fourth transistor N2 is connected to a drain of the second transistor P2. The fifth transistor N3 receives an enable signal ‘en’ at a gate thereof and a drain of the fifth transistor N3 is connected to a node that is connected to a source of the third transistor N1 and a source of the fourth transistor N2 and a source of the fifth transistor N3 is connected to a ground terminal VSS. At this time, the inverted input signal ‘inb’ is a signal inverting the input signal ‘in’. An output signal ‘outb’ is outputted from a node that is connected to the second transistor P2 and the fourth transistor N2.
An operation of the buffer will be described below.
When the enable signal ‘en’ is enabled at a high level and the input signal ‘in’ is at a high level, the fourth and fifth transistors N2 and N3 are turned on, such that the output signal ‘outb’ is at a low level.
When the enable signal ‘en’ is enabled at a high level and the input signal ‘in’ is at a low level, the first to third transistors P1, P2, and N1 are turned on and the output signal ‘outb’ is at a high level.
However, the buffer having this structure is vulnerable to process variation. More specifically, in the case in which the input signal ‘in’ is at a high level, a time in which the output signal ‘outb’ is transited to a low level may be shorter than a designed time when sizes of the fourth and fifth transistors N2 and N3 are larger than designed values due to the process variation. On the contrary, when sizes of the second and fourth transistors P2 and N2 are smaller than designed values, the time in which the output signal ‘outb’ is transited to a low level is lengthened.
Further, in the case in which the input signal ‘in’ is at a low level, a time in which the output signal ‘outb’ is transited to a high level is shortened or lengthened when the sizes of the first to third transistors P1, P2, and N1 are larger or smaller than designed values due to the process variation. In general, as the size of the transistor that is turned on increases, the transistor outputs a large amount of current and as the size of the transistor decreases, the transistor outputs a small amount of current, such that the above-mentioned problem occurs.
When the transition time of the output signal ‘outb’ is shortened or lengthened, an internal circuit that receives the output signal ‘outb’ may not perform a normal operation, such that operational reliability of the semiconductor memory apparatus decreases. As described above, only the process variation is regarded as a problem in operation of the buffer, but in the case of the buffer, a threshold voltage of the transistor varies by variation of a temperature and a voltage, such that an amount of current that is outputted from the transistor varies. Therefore, the transition time of the output signal may vary. Further, in the case in which the input signal ‘in’ is a clock signal, a clock signal outputted through the buffer may be a clock signal having a duty ratio different from at the time of inputting the buffer.